Logic synthesis - PDFSEARCH.IO - Document Search Engine

Logic synthesis
Results: 291

#	Item
81	Diss. ETH NoBinary Adder Architectures for Cell-Based VLSI and their Synthesis A dissertation submitted to the Add to Reading List Source URL: www.iis.ee.ethz.ch Language: English - Date: 2006-03-07 18:18:41 Computer architecture Computer arithmetic Binary arithmetic Binary logic Digital circuits Carry-select adder Carry-save adder Carry-lookahead adder Field-programmable gate array Adders Electronic engineering Arithmetic
82	Diss. ETH NoBinary Adder Architectures for Cell-Based VLSI and their Synthesis A dissertation submitted to the Add to Reading List Source URL: www.iis.ee.ethz.ch Language: English - Date: 2006-03-07 18:19:07 Computer architecture Computer arithmetic Binary arithmetic Binary logic Digital circuits Carry-select adder Carry-save adder Carry-lookahead adder Field-programmable gate array Adders Electronic engineering Arithmetic
83	Corporate Backgrounder Spring 2015 Synopsys Overview and History Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-05-20 16:43:19 Hillsboro Oregon Synopsys Digital electronics Signoff Logic synthesis High-level synthesis Xilinx Magma Design Automation EDA database Electronic engineering Electronic design automation Electronic design
84	2009 19th IEEE International Symposium on Computer Arithmetic Datapath Synthesis for Standard-Cell Design Reto Zimmermann DesignWare, Solutions Group Synopsys Switzerland LLC, 8050 Zurich, Switzerland Add to Reading List Source URL: www.iis.ee.ethz.ch Language: English - Date: 2009-09-17 16:31:54 Computer arithmetic Digital circuits Electronic engineering Binary logic Kogge–Stone adder Binary arithmetic Wallace tree Canonical form Addition Adders Computer architecture Arithmetic
85	PDF Document Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2011-04-14 06:00:26 Electronic design Hardware verification languages SystemC Verilog Register-transfer level High-level synthesis Logic synthesis VHDL Integrated circuit design Electronic engineering Electronic design automation Hardware description languages
86	Enhanced Reliability Design Automation Methodology considering the Generation of Parallel CRC Modules based on arbitrary CRC Polynomials and unlimited Data-Word Widths Timo Brenningmeyer University of Applied Sciences Os Add to Reading List Source URL: www.ecs.hs-osnabrueck.de Language: English - Date: 2012-04-13 13:29:50 Hardware description language Cyclic redundancy check Verilog Logic synthesis High-level synthesis CRC Register-transfer level Checksum Cksum Electronic engineering Electronic design automation Digital electronics
87	Success Story Synopsys and Ricoh Ricoh Optimizes New Multi-Function Printer SoC Architecture with Synopsys Platform Architect MCO Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-05-06 20:16:14 Hardware verification languages Hillsboro Oregon Synopsys High-level synthesis SystemC System on a chip Logic synthesis Ricoh Electronic engineering Electronic design automation Electronic design
88	Type Synthesis for the Logical Solver: an Approach based on Query Automata Louis Jachiet, Pierre Genev`es, Nabil Laya¨ıda July 25, Add to Reading List Source URL: typex.lri.fr Language: English - Date: 2014-06-10 11:53:41 Philosophy of mind Semantics Logic Linguistics Philosophy Interpretation Model theory Philosophy of language
89	Synopsys Automotive Electronics Overview Overview Advanced electronics continue to permeate all aspects of automotive Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-03-20 15:15:42 Digital electronics Hillsboro Oregon Synopsys Embedded system Field-programmable gate array Logic synthesis Automotive electronics Electronic design automation Reliability engineering Electronic engineering Design Electronic design
90	LusSy: an open Tool for the Analysis of Systems-on-aChip at the Transaction Level Matthieu Moy∗ , Florence Maraninchi* , Laurent Maillet-Contoz† Abstract. We describe a toolbox for the analysis of Systems-on-a-chip w Add to Reading List Source URL: www-verimag.imag.fr Language: English - Date: 2007-12-17 11:12:12 Electronic design automation SystemC Logic design Transaction-level modeling High-level synthesis VHDL Advanced Learning and Research Institute Verilog Catapult C Electronic engineering Hardware description languages Digital electronics

UPDATE